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19-1688; Rev 0; 5/00
300ksps/400ksps, Single-Supply, 4-Channel, Serial 12-Bit ADCs with Internal Reference
General Description
The MAX1282/MAX1283 12-bit analog-to-digital converters (ADCs) combine a 4-channel analog-input multiplexer, high-bandwidth track/hold (T/H), and serial interface with high conversion speed and low power consumption. The MAX1282 operates from a single +4.5V to +5.5V supply; the MAX1283 operates from a single +2.7V to +3.6V supply. Both devices' analog inputs are software configurable for unipolar/bipolar and single-ended/pseudo-differential operation. The 4-wire serial interface connects directly to SPITM/QSPITM/MICROWIRETM devices without external logic. A serial strobe output allows direct connection to TMS320-family digital signal processors. The MAX1282/ MAX1283 use an external serial-interface clock to perform successive-approximation analog-to-digital conversions. The devices feature an internal +2.5V reference and a reference-buffer amplifier with a 1.5% voltage-adjustment range. An external reference with a 1V to VDD range may also be used. The MAX1282/MAX1283 provide a hardwired SHDN pin and four software-selectable power modes (normal operation, reduced power (REDP), fast power-down (FASTPD), and full power-down (FULLPD)). These devices can be programmed to automatically shut down at the end of a conversion or to operate with reduced power. When using the power-down modes, accessing the serial interface automatically powers up the devices, and the quick turnon time allows them to be shut down between all conversions. The MAX1282/MAX1283 are available in 16-pin TSSOP packages.
Features
o 4-Channel Single-Ended or 2-Channel Pseudo-Differential Inputs o Internal Multiplexer and Track/Hold o Single-Supply Operation +4.5V to +5.5V (MAX1282) +2.7V to +3.6V (MAX1283) o Internal +2.5V Reference o 400kHz Sampling Rate (MAX1282) o Low Power: 2.5mA (400ksps) 1.3mA (REDP) 0.9mA (FASTPD) 2A (FULLPD) o SPI/QSPI/MICROWIRE/TMS320-Compatible 4-Wire Serial Interface o Software-Configurable Unipolar or Bipolar Inputs o 16-Pin TSSOP Package
MAX1282/MAX1283
Ordering Information
PART MAX1282BCUE MAX1282BEUE MAX1283BCUE MAX1283BEUE TEMP. RANGE 0C to +70C -40C to +85C 0C to +70C -40C to +85C PINPACKAGE 16 TSSOP 16 TSSOP 16 TSSOP 16 TSSOP INL (LSB) 1 1 1 1
Applications
Portable Data Logging Data Acquisition Medical Instruments Battery-Powered Instruments Pen Digitizers Process Control
TOP VIEW
VDD1 1 CH0 2 CH1 3 CH2 4 CH3 5 COM 6 SHDN 7
Pin Configuration
16 VDD2 15 SCLK 14 CS
MAX1282/ MAX1283
13 DIN 12 SSTRB 11 DOUT 10 GND 9 REFADJ
Typical Operating Circuit appears at end of data sheet. SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp.
REF 8
TSSOP
________________________________________________________________ Maxim Integrated Products
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300ksps/400ksps, Single-Supply, 4-Channel, Serial 12-Bit ADCs with Internal Reference MAX1282/MAX1283
ABSOLUTE MAXIMUM RATINGS
VDD_ to GND ........................................................... -0.3V to +6V VDD1 to VDD2 ....................................................... -0.3V to +0.3V CH0-CH3, COM to GND .......................... -0.3V to (VDD_ +0.3V) REF, REFADJ to GND ................................ -0.3V to VDD_ +0.3V) Digital Inputs to GND .............................................. -0.3V to +6V Digital Outputs to GND............................. -0.3V to (VDD_ +0.3V) Digital Output Sink Current .................................................25mA Continuous Power Dissipation (TA = +70C) 16-Pin TSSOP (derate 6.7mW/C above +70C) ........ 535mW Operating Temperature Ranges MAX1282BCUE/MAX1283BCUE ....................... 0C to +70C MAX1282BEUE/MAX1283BEUE ..................... -40C to +85C Storage Temperature Range ............................ -60C to +150C Lead Temperature (soldering, 10s) ................................ +300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS--MAX1282
(VDD1 = VDD2 = +4.5V to +5.5V, COM = GND, fOSC = 6.4MHz, 50% duty cycle, 16 clocks/conversion cycle (400ksps), external +2.5V at REF, REFADJ = VDD1, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER DC ACCURACY (Note 1) Resolution Relative Accuracy (Note 2) Differential Nonlinearity Offset Error Gain Error (Note 3) Gain-Error Temperature Coefficient Channel-to-Channel Offset-Error Matching 1.6 0.2 INL DNL No missing codes over temperature 12 1.0 1.0 6.0 6.0 Bits LSB LSB LSB LSB ppm/C LSB SYMBOL CONDITIONS MIN TYP MAX UNITS
DYNAMIC SPECIFICATIONS (100kHz sine-wave input, 2.5Vp-p, 400ksps, 6.4MHz clock, bipolar input mode) Signal-to-Noise plus Distortion Ratio Total Harmonic Distortion Spurious-Free Dynamic Range Intermodulation Distortion Channel-to-Channel Crosstalk (Note 4) Full-Power Bandwidth Full-Linear Bandwidth CONVERSION RATE Conversion Time (Note 5) Track/Hold Acquisition Time Aperture Delay Aperture Jitter Serial Clock Frequency Duty Cycle fSCLK 0.5 40 tCONV tACQ 10 <50 6.4 60 2.5 400 s ns ns ps MHz % SINAD THD SFDR IMD fIN1 = 99kHz, fIN2 =102kHz 200kHz, VIN = 2.5Vp-p -3dB point SINAD > 68dB Up to the 5th harmonic 70 -81 80 76 -78 6 350 dB dB dB dB dB MHz kHz
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300ksps/400ksps, Single-Supply, 4-Channel, Serial 12-Bit ADCs with Internal Reference MAX1282/MAX1283
ELECTRICAL CHARACTERISTICS--MAX1282 (continued)
(VDD1 = VDD2 = +4.5V to +5.5V, COM = GND, fOSC = 6.4MHz, 50% duty cycle, 16 clocks/conversion cycle (400ksps), external +2.5V at REF, REFADJ = VDD1, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER SYMBOL CONDITIONS Unipolar, VCOM = 0 VCH_ Bipolar, VCOM or VCH_ = VREF/2, referenced to COM or CH_ On/off leakage current, VCOM, VCH_ = 0 or VDD1 0.001 18 VREF TA = +25C 2.480 2.500 15 TC VREF 0 to 1mA output load 4.7 0.01 1.22 For small adjustments, from 1.22V To power down the internal reference 1.4 +2.05 1.0 200 VDD1 + 50mV 350 320 5 3.0 0.8 0.2 VIN = 0 or VDD2 15 ISINK = 5mA ISOURCE = 1mA CS = VDD2 CS = VDD2 15 4 10 0.4 1 V V V A pF V V A pF A 100 VDD1 - 1.0 15 0.05 2.0 10 10 2.520 MIN TYP MAX VREF VREF/2 1 V UNITS ANALOG INPUTS (CH3-CH0, COM) Input Voltage Range, SingleEnded and Differential (Note 6) Multiplexer Leakage Current Input Capacitance INTERNAL REFERENCE REF Output Voltage REF Short-Circuit Current REF Output Temperature Coefficient Load Regulation (Note 7) Capacitive Bypass at REF Capacitive Bypass at REFADJ REFADJ Output Voltage REFADJ Input Range REFADJ Buffer Disable Threshold Buffer Voltage Gain EXTERNAL REFERENCE (reference buffer disabled, reference applied to REF) REF Input Voltage Range (Note 8) VREF = 2.500V, fSCLK = fMAX REF Input Current DIGITAL INPUTS (DIN, SCLK, CS, SHDN) Input High Voltage Input Low Voltage Input Hysteresis Input Leakage Input Capacitance DIGITAL OUTPUTS (DOUT, SSTRB) Output Voltage Low Output Voltage High Three-State Leakage Current Three-State Output Capacitance VOL VOH IL COUT VINH VINL VHYST IIN CIN VREF = 2.500V, fSCLK = 0 In full power-down mode, fSCLK = 0 V V mA ppm/C mV/mA F F V mV V V/V
A pF
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300ksps/400ksps, Single-Supply, 4-Channel, Serial 12-Bit ADCs with Internal Reference MAX1282/MAX1283
ELECTRICAL CHARACTERISTICS--MAX1282 (continued)
(VDD1 = VDD2 = +4.5V to +5.5V, COM = GND, fOSC = 6.4MHz, 50% duty cycle, 16 clocks/conversion cycle (400ksps), external +2.5V at REF, REFADJ = VDD1, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER POWER SUPPLY Positive Supply Voltage (Note 9) VDD1, VDD2 Normal operating mode (Note 10) Supply Current IVDD1+ IVDD2 PSR VDD1 = VDD2 = 5.5V Reduced-power mode (Note 11) Fast power-down mode (Note 11) Full power-down mode (Note 11) Power-Supply Rejection VDD1 = VDD2 = 5V 10%, midscale input 4.5 2.5 1.3 0.9 2.0 0.5 5.5 4.0 2.0 1.5 10 2.0 A mV mA V SYMBOL CONDITIONS MIN TYP MAX UNITS
ELECTRICAL CHARACTERISTICS--MAX1283
(VDD1 = VDD2 = +2.7V to +3.6V, COM = GND, fOSC = 4.8MHz, 50% duty cycle, 16 clocks/conversion cycle (300ksps), external +2.5V at REF, REFADJ = VDD1, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER DC ACCURACY (Note 1) Resolution Relative Accuracy (Note 2) Differential Nonlinearity Offset Error Gain Error (Note 3) Gain-Error Temperature Coefficient Channel-to-Channel Offset-Error Matching 1.6 0.2 INL DNL No missing codes over temperature 12 1.0 1.0 6.0 6.0 Bits LSB LSB LSB LSB ppm/C LSB SYMBOL CONDITIONS MIN TYP MAX UNITS
DYNAMIC SPECIFICATIONS (100kHz sine-wave input, 2.5Vp-p, 400ksps, 6.4MHz clock, bipolar input mode) Signal-to-Noise plus Distortion Ratio Total Harmonic Distortion Spurious-Free Dynamic Range Intermodulation Distortion Channel-to-Channel Crosstalk (Note 4) Full-Power Bandwidth Full-Linear Bandwidth SINAD THD SFDR IMD fIN1 = 73kHz, fIN2 = 77kHz f = 150kHz, VIN = 2.5Vp-p -3dB point SINAD > 68dB Up to the 5th harmonic 70 -70 72 76 -78 3 250 dB dB dB dB dB MHz kHz
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300ksps/400ksps, Single-Supply, 4-Channel, Serial 12-Bit ADCs with Internal Reference
ELECTRICAL CHARACTERISTICS--MAX1283 (continued)
(VDD1 = VDD2 = +2.7V to +3.6V, COM = GND, fOSC = 4.8MHz, 50% duty cycle, 16 clocks/conversion cycle (300ksps), external +2.5V at REF, REFADJ = VDD1, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER CONVERSION RATE Conversion Time (Note 5) Track/Hold Acquisition Time Aperture Delay Aperture Jitter Serial Clock Frequency Duty Cycle ANALOG INPUTS (CH3-CH0, COM) Input Voltage Range, Single Ended and Differential (Note 6) Multiplexer Leakage Current Input Capacitance INTERNAL REFERENCE REF Output Voltage REF Short-Circuit Current REF Output Temperature Coefficient Load Regulation (Note 7) Capacitive Bypass at REF Capacitive Bypass at REFADJ REFADJ Output Voltage REFADJ Input Range REFADJ Buffer Disable Threshold Buffer Voltage Gain EXTERNAL REFERENCE (reference buffer disabled, reference applied to REF) Buffer Voltage Gain REF Input Voltage Range (Note 8) VREF = 2.500V, fSCLK = fMAX REF Input Current DIGITAL INPUTS (DIN, SCLK, CS, SHDN) Input High Voltage Input Low Voltage Input Hysteresis Input Leakage Input Capacitance VINH VINL VHYST IIN CIN VIN = 0 or VDD2 15 0.2 1 2.0 0.8 V V V A pF VREF = 2.500V, fSCLK = 0 In full power-down mode, fSCLK = 0 1.0 200 For small adjustments, from 1.22V To power down the internal reference 1.4 2.05 2.05 VDD1 + 50mV 350 320 5 A TC VREF 0 to 0.75mA output load 4.7 0.01 1.22 100 VDD1 - 1.0 VREF TA = +25C 2.480 2.500 15 15 0.1 2.0 10 10 2.520 V mA ppm/C mV/mA F F V mV V V/V V/V V Unipolar, VCOM = 0 VCH_ Bipolar, VCOM or VCH_ = VREF/2, referenced to COM or CH_ On/off leakage current, VCH_ = 0 or VDD1 0.001 18 VREF VREF/2 1 V A pF fSCLK Normal operating mode 0.5 40 tCONV tACQ Normal operating mode Normal operating mode 10 <50 4.8 60 3.3 625 s ns ns ps MHz % SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX1282/MAX1283
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300ksps/400ksps, Single-Supply, 4-Channel, Serial 12-Bit ADCs with Internal Reference MAX1282/MAX1283
ELECTRICAL CHARACTERISTICS--MAX1283 (continued)
(VDD1 = VDD2 = +2.7V to +3.6V, COM = GND, fOSC = 4.8MHz, 50% duty cycle, 16 clocks/conversion cycle (300ksps), external +2.5V at REF, REFADJ = VDD1, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER Output Voltage Low Output Voltage High Three-State Leakage Current Three-State Output Capacitance POWER SUPPLY Positive Supply Voltage (Note 9) VDD1, VDD2 Normal operating mode (Note 10) Supply Current IVDD1 + IVDD2 PSR VDD1 = VDD2 = 3.6V Reduced-power mode (Note 11) Fast power-down mode (Note 11) Full power-down mode (Note 11) Power-Supply Rejection VDD1 = VDD2 = 2.7V to 3.6V, midscale input 2.7 2.5 1.3 0.9 2.0 0.5 3.6 3.5 2.0 1.5 10 2.0 A mV mA V SYMBOL VOL VOH IL COUT ISINK = 5mA ISOURCE = 0.5mA CS = VDD2 CS = VDD2 15 VDD2 - 0.5V 10 CONDITIONS MIN TYP MAX 0.4 UNITS V V A pF DIGITAL OUTPUTS (DOUT, SSTRB)
TIMING CHARACTERISTICS--MAX1282
(Figures 1, 2, 5, 6; VDD1 = VDD2 = +4.5V to +5.5V, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SCLK Period SCLK Pulse Width High SCLK Pulse Width Low DIN to SCLK Setup DIN to SCLK Hold CS Fall to SCLK Rise Setup SCLK Rise to CS Rise Hold SCLK Rise to CS Fall Ignore CS Rise to SCLK Rise Ignore SCLK Rise to DOUT Hold SCLK Rise to SSTRB Hold SCLK Rise to DOUT Valid SCLK Rise to SSTRB Valid CS Rise to DOUT Disable CS Rise to SSTRB Disable CS Fall to DOUT Enable CS Fall to SSTRB Enable CS Pulse Width High SYMBOL tCP tCH tCL tDS tDH tCSS tCSH tCSO tCS1 tDOH tSTH tDOV tSTV tDOD tSTD tDOE tSTE tCSW CLOAD = 20pF CLOAD = 20pF CLOAD = 20pF CLOAD = 20pF CLOAD = 20pF CLOAD = 20pF CLOAD = 20pF CLOAD = 20pF 100 10 10 CONDITIONS MIN 156 62 62 35 0 35 0 35 35 10 10 20 20 80 80 65 65 65 65 TYP MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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300ksps/400ksps, Single-Supply, 4-Channel, Serial 12-Bit ADCs with Internal Reference MAX1282/MAX1283
TIMING CHARACTERISTICS--MAX1283
(Figures 1, 2, 5, 6; VDD1 = VDD2 = +2.7V to +3.6V, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SCLK Period SCLK Pulse Width High SCLK Pulse Width Low DIN to SCLK Setup DIN to SCLK Hold CS Fall to SCLK Rise Setup SCLK Rise to CS Rise Hold SCLK Rise to CS Fall Ignore CS Rise to SCLK Rise Ignore SCLK Rise to DOUT Hold SCLK Rise to SSTRB Hold SCLK Rise to DOUT Valid SCLK Rise to SSTRB Valid CS Rise to DOUT Disable CS Rise to SSTRB Disable CS Fall to DOUT Enable CS Fall to SSTRB Enable CS Pulse Width High SYMBOL tCP tCH tCL tDS tDH tCSS tCSH tCSO tCS1 tDOH tSTH tDOV tSTV tDOD tSTD tDOE tSTE tCSW CLOAD = 20pF CLOAD = 20pF CLOAD = 20pF CLOAD = 20pF CLOAD = 20pF CLOAD = 20pF CLOAD = 20pF CLOAD = 20pF 100 13 13 CONDITIONS MIN 208 83 83 45 0 45 0 45 45 13 13 20 20 100 100 85 85 85 85 TYP MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note 1: Tested at VDD1 = VDD2 = VDD(MIN), COM = GND, unipolar single-ended input mode. Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has been calibrated. Note 3: Offset nulled. Note 4: Ground the "on" channel; sine wave is applied to all "off" channels. Note 5: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle. Note 6: The common-mode range for the analog inputs (CH3-CH0 and COM) is from GND to VDD1. Note 7: External load should not change during conversion for specified accuracy. Note 8: ADC performance is limited by the converter's noise floor, typically 300Vp-p. An external reference below 2.5V compromises the performance of the ADC. Note 9: Electrical characteristics are guaranteed from VDD1(MIN) = VDD2(MIN) to VDD1(MAX) = VDD2(MIN). For operations beyond this range, see Typical Operating Characteristics. For guaranteed specifications beyond the limits, contact the factory. Note 10: AIN = midscale, unipolar mode. MAX1282 tested with 20pF on DOUT, 20pF on SSTRB, and fSCLK = 6.4MHz, 0 to 5V. MAX1283 tested with same loads, fSCLK = 4.8MHz, 0 to 3V. Note 11: SCLK = DIN = GND, CS = VDD1.
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300ksps/400ksps, Single-Supply, 4-Channel, Serial 12-Bit ADCs with Internal Reference MAX1282/MAX1283
Typical Operating Characteristics
(MAX1282: VDD1 = VDD2 = 5.0V, fSCLK = 6.4MHz; MAX1283: VDD1 = VDD2 = 3.0V, fSCLK = 4.8MHz; CLOAD = 20pF, 4.7F capacitor at REF, 0.01F capacitor at REFADJ, TA = +25C, unless otherwise noted.)
INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE
MAX1280/1-01
DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE
0.4 0.3 0.2 DNL (LSB)
MAX1280/1-02
SUPPLY CURRENT vs. SUPPLY VOLTAGE (CONVERTING)
MAX1282/3-03
0.4 0.3 0.2 INL (LSB) 0.1 0 -0.1 -0.2 -0.3 -0.4 0
0.5
3.5
0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5
SUPPLY CURRENT (mA)
3.0
2.5
2.0
1.5 0 500 1000 1500 2000 2500 3000 3500 4000 4500 DIGITAL OUTPUT CODE 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V)
500 1000 1500 2000 2500 3000 3500 4000 4500 DIGITAL OUTPUT CODE
SUPPLY CURRENT vs. TEMPERATURE
MAX1282/3-04
SUPPLY CURRENT vs. SUPPLY VOLTAGE (STATIC)
MAX1282/3-05
SUPPLY CURRENT vs. TEMPERATURE (STATIC)
MAX1282/3-06
3.2 3.0 SUPPLY CURRENT (mA) 2.8 2.6 2.4 MAX1283 2.2 2.0 -40 -20 0 20 40 60 80 MAX1282
2.5 NORMAL OPERATION (PD1 = PD0 = 1)
2.5 MAX1282 (PD1 = 1, PD0 = 1) MAX1283 (PD1 = 1, PD0 = 1) 1.5 MAX1282 (PD1 = 1, PD0 = 0) MAX1283 (PD1 = 1, PD0 = 0)
2.0 SUPPLY CURRENT (mA)
2.0 SUPPLY CURRENT (mA)
1.5
REDP (PD1 = 1, PD0 = 0)
1.0 FASTDP (PD1 = 0, PD0 = 1) 0.5
1.0
0.5
MAX1282 (PD1 = 0, PD0 = 1) MAX1283 (PD1 = 0, PD0 = 1)
0 100 2.5 3.0 3.5 4.0 4.5 5.0 5.5 TEMPERATURE (C) SUPPLY VOLTAGE (V)
0 -40 -20 0 20 40 60 80 100 TEMPERATURE (C)
SHUTDOWN CURRENT vs. SUPPLY VOLTAGE
MAX1282/3-07
SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE
MAX1282/3-08
REFERENCE VOLTAGE vs. SUPPLY VOLTAGE
MAX1282/3-09
5 (PD1 = PD0 = 0) 4 SUPPLY CURRENT (A)
2.5 (PD1 = PD0 = 0) 2.0 SUPPLY CURRENT (A) MAX1282
2.5005
2.5003 REFERENCE VOLTAGE (V)
3
1.5 MAX1283
2.5001
2
1.0
2.4999
1
0.5
2.4997
0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V)
0 -40 -20 0 20 40 60 80 100 TEMPERATURE (C)
2.4995 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V)
8
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300ksps/400ksps, Single-Supply, 4-Channel, Serial 12-Bit ADCs with Internal Reference MAX1282/MAX1283
Typical Operating Characteristics (continued)
(MAX1282: VDD1 = VDD2 = 5.0V, fSCLK = 6.4MHz; MAX1283: VDD1 = VDD2 = 3.0V, fSCLK = 4.8MHz; CLOAD = 20pF, 4.7F capacitor at REF, 0.01F capacitor at REFADJ, TA = +25C, unless otherwise noted.)
REFERENCE VOLTAGE vs. TEMPERATURE
MAX1282/3-10
OFFSET ERROR vs. SUPPLY VOLTAGE
MAX1282/3-11
OFFSET ERROR vs. TEMPERATURE
MAX1282/3-12
2.5002 2.5000 MAX1282 REFERENCE VOLTAGE (V) 2.4998 2.4996 2.4994 2.4992 2.4990 2.4988 -40 -20 0 20 40 60 80 MAX1283
2.0 1.5 OFFSET ERROR (LSB) 1.0
0.5 0 OFFSET ERROR (LSB) -0.5 -1.0 -1.5 -2.0 -2.5 -40 -15 10 35 60
0.5 0 -0.5 -1.0 -1.5 -2.0
100
2.5
3.0
3.5
4.0
4.5
5.0
5.5
85
TEMPERATURE (C)
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
GAIN ERROR vs. SUPPLY VOLTAGE
0.8 0.6 GAIN ERROR (LSB) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V) -2.0 -40 -1.5
MAX1282/3-13
GAIN ERROR vs. TEMPERATURE
MAX1282/3-14
1.0
0.5
0 GAIN ERROR (LSB)
-0.5
-1.0
-15
10
35
60
85
TEMPERATURE (C)
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300ksps/400ksps, Single-Supply, 4-Channel, Serial 12-Bit ADCs with Internal Reference MAX1282/MAX1283
Pin Description
PIN 1 2-5 6 7 NAME VDD1 CH0-CH3 COM SHDN Positive Supply Voltage Sampling Analog Inputs Ground Reference for Analog Inputs. COM sets zero-code voltage in single-ended mode. Must be stable to 0.5LSB. Active-Low Shutdown Input. Pulling SHDN low shuts down the device, reducing supply current to 2A (typ). Reference-Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion. In internal reference mode, the reference buffer provides a 2.500V nominal output, externally adjustable at REFADJ. In external reference mode, disable the internal buffer by pulling REFADJ to VDD1. Input to the Reference-Buffer Amplifier. To disable the reference-buffer amplifier, connect REFADJ to VDD1. Ground Serial-Data Output. Data is clocked out at SCLK's rising edge. High impedance when CS is high. Serial Strobe Output. SSTRB pulses high for one clock period before the MSB decision. High impedance when CS is high. Serial-Data Input. Data is clocked in at SCLK's rising edge. Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT and SSTRB are high impedance. Serial-Clock Input. Clocks data in and out of serial interface and sets the conversion speed. (Duty cycle must be 40% to 60%.) Positive Supply Voltage FUNCTION
8
REF
9 10 11 12 13 14 15 16
REFADJ GND DOUT SSTRB DIN CS SCLK VDD2
VDD2
VDD2 3k DOUT CLOAD 70pF GND a) VOH to High-Z DOUT CLOAD 20pF GND b) VOL to High-Z
DOUT CLOAD 50pF GND a) High-Z to VOH and VOL to VOH
DOUT
3k
3k
CLOAD 50pF GND b) High-Z to VOL and VOH to VOL
3k
Figure 1. Load Circuits for Enable Time 10
Figure 2. Load Circuits for Disable Time
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300ksps/400ksps, Single-Supply, 4-Channel, Serial 12-Bit ADCs with Internal Reference
Detailed Description
The MAX1282/MAX1283 ADCs use a successiveapproximation conversion technique and input T/H circuitry to convert an analog signal to a 12-bit digital output. A flexible serial interface provides easy interface to microprocessors (Ps). Figure 3 shows a functional diagram of the MAX1282/MAX1283. sinusoidal signal at IN-, the input voltage is determined by: IN - = (VIN - ) sin(2ft) The maximum voltage variation is determined by: max d( IN - ) dt = VIN - 2f 1LSB VREF = 12 t CONV 2 t CONV
MAX1282/MAX1283
Pseudo-Differential Input
The equivalent circuit of Figure 4 shows the MAX1282/ MAX1283's input architecture, which is composed of a T/H, input multiplexer, input comparator, switchedcapacitor DAC, and reference. In single-ended mode, the positive input (IN+) is connected to the selected input channel and the negative input (IN-) is set to COM. In differential mode, IN+ and IN- are selected from the following pairs: CH0/CH1 and CH2/CH3. Configure the channels according to Tables 1 and 2. The MAX1282/MAX1283 input configuration is pseudodifferential because only the signal at IN+ is sampled. The return side (IN-) is connected to the sampling capacitor while converting and must remain stable within 0.5LSB (0.1LSB for best results) with respect to GND during a conversion. If a varying signal is applied to the selected IN-, its amplitude and frequency must be limited to maintain accuracy. The following equations express the relationship between the maximum signal amplitude and its frequency to maintain 0.5LSB accuracy. Assuming a
A 0.65Vp-p, 60Hz signal at IN- will generate a 0.5LSB error when using a +2.5V reference voltage and a 2.5s conversion time (15 / fSCLK). When a DC reference voltage is used at IN-, connect a 0.1F capacitor to GND to minimize noise at the input. During the acquisition interval, the channel selected as the positive input (IN+) charges capacitor CHOLD. The acquisition interval spans three SCLK cycles and ends on the falling SCLK edge after the input control word's last bit has been entered. At the end of the acquisition interval, the T/H switch opens, retaining charge on CHOLD as a sample of the signal at IN+. The conversion interval begins with the input multiplexer switching CHOLD from IN+ to IN-. This unbalances node ZERO at the comparator's input. The capacitive DAC adjusts during the remainder of the conversion cycle to restore node ZERO to VDD1 / 2 within the limits of 12-bit resolution. This action is equivalent to transferring a 12pF (VIN+ - VIN-) charge from CHOLD to the binaryweighted capacitive DAC, which in turn forms a digital representation of the analog input signal.
GND
CS SCLK DIN SHDN CH0 CH1 CH2 CH3
14 15 13 7 2 3 4 5 INPUT SHIFT REGISTER INT CLOCK CONTROL LOGIC OUTPUT SHIFT REGISTER ANALOG INPUT MUX T/H CLOCK IN 12-BIT SAR ADC OUT REF 17k A 2.05 11 12 DOUT SSTRB CH0 CH1 CH2 CH3 COM
REF INPUT MUX
CAPACITIVE DAC CHOLD 12pF ZERO COMPARATOR
CSWITCH* 6pF HOLD
RIN 800 TRACK AT THE SAMPLING INSTANT, THE MUX INPUT SWITCHES FROM THE SELECTED IN+ CHANNEL TO THE SELECTED IN- CHANNEL.
COM
6 +1.22V REFERENCE
1 16 10
VDD1 VDD2 GND
REFADJ REF
9 8 +2.500V
MAX1282 MAX1283
VDD1/2 SINGLE-ENDED MODE: IN+ = CH0-CH3, IN- = COM. PSEUDO-DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF CH0/CH1 AND CH2/CH3. *INCLUDES ALL INPUT PARASITICS
Figure 3. Functional Diagram
Figure 4. Equivalent Input Circuit 11
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300ksps/400ksps, Single-Supply, 4-Channel, Serial 12-Bit ADCs with Internal Reference MAX1282/MAX1283
Table 1. Channel Selection in Single-Ended Mode (SGL/DIF = 1)
SEL2 0 1 0 1 SEL1 0 0 1 1 SEL0 1 1 0 0 CH0 + CH1 + + + CH2 CH3 COM - - - -
Table 2. Channel Selection in Pseudo-Differential Mode (SGL/DIF = 0)
SEL2 0 0 1 1 SEL1 0 1 0 1 SEL0 1 0 1 0 - + - + CH0 + CH1 - + - CH2 CH3
Track/Hold
The T/H enters its tracking mode on the falling clock edge after the fifth bit of the 8-bit control word has been shifted in. It enters its hold mode on the falling clock edge after the eighth bit of the control word has been shifted in. If the converter is set up for single-ended inputs, IN- is connected to COM and the converter samples the "+" input. If the converter is set up for differential inputs, the difference of [(IN+) - (IN-)] is converted. At the end of the conversion, the positive input connects back to IN+ and CHOLD charges to the input signal. The time required for the T/H to acquire an input signal is a function of how quickly its input capacitance is charged. If the input signal's source impedance is high, the acquisition time lengthens, and more time must be allowed between conversions. The acquisition time, tACQ, is the maximum time the device takes to acquire the signal and the minimum time needed for the signal to be acquired. It is calculated by the following equation: tACQ = 9 (RS + RIN) 18pF where RIN = 800 and RS = the source impedance of the input signal; t ACQ is never less than 400ns (MAX1282) or 625ns (MAX1283). Note that source impedances below 2k do not significantly affect the ADC's AC performance.
events and measure periodic signals with bandwidths exceeding the ADC's sampling rate by using undersampling techniques. To avoid high-frequency signals being aliased into the frequency band of interest, antialias filtering is recommended.
Analog Input Protection
Internal protection diodes, which clamp the analog input to VDD1 and GND, allow the channel input pins to swing from GND - 0.3V to V DD1 + 0.3V without damage. However, for accurate conversions near full scale, the inputs must not exceed VDD1 by more than 50mV or be lower than GND by 50mV. If the analog input exceeds 50mV beyond the supplies, do not allow the input current to exceed 2mA.
Starting a Conversion
Start a conversion by clocking a control byte into DIN. With CS low, each rising edge on SCLK clocks a bit from DIN into the MAX1282/MAX1283's internal shift register. After CS falls, the first arriving logic "1" bit defines the control byte's MSB. Until this first "start" bit arrives, any number of logic "0" bits can be clocked into DIN with no effect. Table 3 shows the control-byte format. The MAX1282/MAX1283 are compatible with SPI/ QSPI/MICROWIRE devices. For SPI, select the correct clock polarity and sampling edge in the SPI control registers: set CPOL = 0 and CPHA = 0. MICROWIRE, SPI, and QSPI all transmit a byte and receive a byte at the same time. Using the Typical Operating Circuit, the simplest software interface requires only three 8-bit transfers to perform a conversion (one 8-bit transfer to configure the ADC, and two more 8-bit transfers to clock out the
Input Bandwidth
The ADC's input tracking circuitry has a 6MHz (MAX1282) or 3MHz (MAX1283) small-signal bandwidth, so it is possible to digitize high-speed transient
12
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300ksps/400ksps, Single-Supply, 4-Channel, Serial 12-Bit ADCs with Internal Reference
conversion result). (See Figure 16 for MAX1282/ MAX1283 QSPI connections.) Simple Software Interface Make sure the CPU's serial interface runs in master mode so the CPU generates the serial clock. Choose a clock frequency from 500kHz to 6.4MHz (MAX1282) or 4.8MHz (MAX1283). 1) Set up the control byte and call it TB1. TB1 should be in the format: 1XXXXXXX binary, where the Xs denote the particular channel, selected conversion mode, and power mode. 2) Use a general-purpose I/O line on the CPU to pull CS low. 3) Transmit TB1 and, simultaneously, receive a byte and call it RB1. Ignore RB1. 4) Transmit a byte of all zeros ($00 hex) and, simultaneously, receive byte RB2. 5) Transmit a byte of all zeros ($00 hex) and, simultaneously, receive byte RB3. 6) Pull CS high. Figure 5 shows the timing for this sequence. Bytes RB2 and RB3 contain the result of the conversion, padded with three leading zeros, and one trailing zero. The total conversion time is a function of the serial-clock frequency and the amount of idle time between 8-bit transfers. To avoid excessive T/H droop, make sure the total conversion time does not exceed 120s. Digital Output In unipolar input mode, the output is straight binary (Figure 13). For bipolar input mode, the output is two's complement (Figure 14). Data is clocked out on the rising edge of SCLK in MSB-first format.
Data Framing
The falling edge of CS does not start a conversion. The first logic high clocked into DIN is interpreted as a start bit and defines the first bit of the control byte. A conversion starts on SCLK's falling edge, after the eighth bit of the control byte (the PD0 bit) is clocked into DIN. The start bit is defined as follows: The first high bit clocked into DIN with CS low any time the converter is idle, e.g., after VDD1 and VDD2 are applied. or The first high bit clocked into DIN after B6 of a conversion in progress is clocked onto the DOUT pin (Figure 7). Once a start bit has been recognized, the current conversion may only be terminated by pulling SHDN low. The fastest the MAX1282/MAX1283 can run with CS held low between conversions is 16 clocks per conversion. Figure 7 shows the serial-interface timing necessary to perform a conversion every 16 SCLK cycles. If CS is tied low and SCLK is continuous, guarantee a start bit by first clocking in 16 zeros.
MAX1282/MAX1283
___________Applications Information
Power-On Reset
When power is first applied, and if SHDN is not pulled low, internal power-on reset circuitry activates the MAX1282/MAX1283 in normal operating mode, ready to convert with SSTRB = low. After the power supplies stabilize, the internal reset time is 10s, and no conversions should be performed during this phase. If CS is low, the first logic 1 on DIN is interpreted as a start bit. Until a conversion takes place, DOUT shifts out zeros. Additionally, wait for the reference to stabilize when using the internal reference.
Serial Clock
The external clock not only shifts data in and out, but it also drives the analog-to-digital conversion steps. SSTRB pulses high for one clock period after the last bit of the control byte. Successive-approximation bit decisions are made and appear at DOUT on each of the next 12 SCLK rising edges, MSB first (Figure 5). SSTRB and DOUT go into a high-impedance state when CS goes high; after the next CS falling edge, SSTRB outputs a logic low. Figure 6 shows the detailed serial-interface timings. The conversion must complete in 120s or less, or droop on the sample-and-hold capacitors may degrade conversion results.
Power Modes
Save power by placing the converter in one of two lowcurrent operating modes or in full power-down between conversions. Select the power-down mode through bit 1 and bit 0 of the DIN control byte (Tables 3 and 4), or force the converter into hardware shutdown by driving SHDN to GND. The software power-down modes take effect after the conversion is completed; SHDN overrides any software power mode and immediately stops any conversion in progress. In software power-down mode, the serial interface remains active while waiting for a new control byte to start conversion and switch to full-power mode.
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13
300ksps/400ksps, Single-Supply, 4-Channel, Serial 12-Bit ADCs with Internal Reference MAX1282/MAX1283
Table 3. Control-Byte Format
BIT 7 (MSB) START BIT 7(MSB) 6 5 4 3 BIT 6 SEL2 NAME START SEL2 SEL1 SEL0 UNI/BIP BIT 5 SEL1 DESCRIPTION The first logic 1 bit after CS goes low defines the beginning of the control byte. These three bits select which of the eight channels are used for the conversion (Tables 1 and 2). BIT 4 SEL0 BIT 3 UNI/BIP BIT 2 SGL/DIF BIT 1 PD1 BIT 0 (LSB) PD0
1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, an analog input signal from 0 to VREF can be converted; in bipolar mode, the differential signal can range from -VREF/2 to +VREF/2. 1 = single ended, 0 = pseudo-differential. Selects single-ended or pseudo-differential conversions. In single-ended mode, input signal voltages are referred to COM. In pseudo-differential mode, the voltage difference between two channels is measured (Tables 1 and 2). Select operating mode. PD1 PD0 Mode 0 0 Full power-down 0 1 Fast power-down 1 0 Reduced power 1 1 Normal operation
2
SGL/DIF
1 0(LSB)
PD1 PD0
Table 4. Software-Controlled Power Modes
TOTAL SUPPLY CURRENT PD1/PD0 MODE CONVERTING (mA) 2.5 2.5 2.5 2.5 AFTER CONVERSION 2A 0.9mA 1.3mA 2.0mA CIRCUIT SECTIONS* INPUT COMPARATOR Off Reduced Power Reduced Power Full Power REFERENCE Off On On On
00 01 10 11
Full Power-Down (FULLPD) Fast Power-Down (FASTPD) Reduced-Power Mode (REDP) Normal Operating
*Circuit operation between conversions; during conversion all circuits are fully powered up.
Once conversion is completed, the device goes into the programmed power mode until a new control byte is written. The power-up delay is dependent on the power-down state. Software low-power modes will be able to start conversion immediately when running at decreased clock rates (see Power-Down Sequencing). Upon power-on reset, when exiting software full power-down mode, or when exiting hardware shutdown, the device goes immediately into full-power mode and is ready to
14
convert after 2s when using an external reference. When using the internal reference, wait for the typical power-up delay from a full power-down (software or hardware) as shown in Figure 8. Software Power-Down Software power-down is activated using bits PD1 and PD0 of the control byte. When software power-down is asserted, the ADC completes the conversion in
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300ksps/400ksps, Single-Supply, 4-Channel, Serial 12-Bit ADCs with Internal Reference MAX1282/MAX1283
CS
tACQ SCLK 1 4 8 9 12 16 20 24
DIN
SEL SEL SEL UNI/ SGL/ 2 1 0 BIP DIF PD2 PD2 START
SSTRB RB1 RB2 B11 B10 B9 B8 B7 DOUT A/D STATE IDLE 400ns (CLK = 6.4MHz) CONVERSION IDLE B6 RB3 B5 B4 B3 B2 B1 B0
Figure 5. Single-Conversion Timing
progress and powers down into the specified low-quiescent-current state (2A, 0.9mA, or 1.3mA). The first logic 1 on DIN is interpreted as a start bit and puts the MAX1282/MAX1283 into its full-power mode. Following the start bit, the data input word or control byte also determines the next power-down state. For example, if the DIN word contains PD1 = 0 and PD0 = 1, a 0.9mA power-down resumes after one conversion. Table 4 details the four power modes with the corresponding supply current and operating sections. Hardware Power-Down Pulling SHDN low places the converter in hardware power-down. Unlike software power-down mode, the conversion is not completed; it stops coincidentally with SHDN being brought low. When returning to normal operation--from SHDN, with an external reference--the MAX1282/MAX1283 can be considered fully powered up within 2s of actively pulling SHDN high. When using the internal reference, the conversion should be initiated only when the reference has settled; its recovery time is dependent on the external bypass capacitors and the time between conversions.
and power-down modes may attain the lowest power consumption in other applications. Using Full Power-Down Mode Full power-down mode (FULLPD) achieves the lowest power consumption, up to 1000 conversions per channel per second. Figure 9a shows the MAX1283's power consumption for one- or four-channel conversions utilizing full power-down mode (PD1 = PD0 = 0), with the internal reference and conversion controlled at the maximum clock speed. A 0.01F bypass capacitor at REFADJ forms an RC filter with the internal 17k reference resistor, with a 170s time constant. To achieve full 12-bit accuracy, nine time constants or 1.5ms are required after power-up if the bypass capacitor is fully discharged between conversions. Waiting this 1.5ms duration in fast power-down (FASTPD) or reducedpower (REDP) mode instead of in full power-up can further reduce power consumption. This is achieved by using the sequence shown in Figure 11a. Figure 9b shows the MAX1283's power consumption for one- or four-channel conversions utilizing FULLPD mode (PD1 = PD0 = 0), with an external reference and conversion controlled at the maximum clock speed. One dummy conversion to power up the device is needed, but no waiting time is necessary to start the second conversion, thereby achieving lower power consumption as low as half the full sampling rate.
Power-Down Sequencing
The MAX1282/MAX1283 auto power-down modes can save considerable power when operating at less than maximum sample rates. Figures 9 and 10 show the average supply current as a function of the sampling rate. The following sections discuss the various powerdown sequences. Other combinations of clock rates
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15
300ksps/400ksps, Single-Supply, 4-Channel, Serial 12-Bit ADCs with Internal Reference MAX1282/MAX1283
CS tCSW tCSS tCSO SCLK tDH tDS DIN tDOH tDOV tDOE DOUT tSTH tSTV tDOD tCL #10 tCH tCP tCSH tCS1
tSTE SSTRB
tSTD
Figure 6. Detailed Serial-Interface Timing
Using Fast Power-Down and Reduced-Power Modes FASTPD and REDP modes achieve the lowest power consumption at speeds close to the maximum sampling rate. Figure 10 shows the MAX1283's power consumption in FASTPD mode (PD1 = 0, PD0 = 1), REDP mode (PD1 = 1, PD0 = 0), and, for comparison, normal operating mode (PD1 = 1, PD0 = 1). The figure shows power consumption using the specified powerdown mode, with the internal reference and conversion controlled at the maximum clock speed. The clock speed in FASTPD or REDP should be limited to 4.8MHz for the MAX1282/MAX1283. FULLPD mode may provide increased power savings in applications where the MAX1282/MAX1283 are inactive for long periods of time, but intermittent bursts of high-speed conversions are required. Figure 11b shows FASTPD and REDP timing.
An internal buffer is designed to provide 2.5V at REF for the MAX1282/MAX1283. The internally trimmed 1.22V reference is buffered with a 2.05 gain. Internal Reference The MAX1282/MAX1283's full-scale range with the internal reference is 2.5V with unipolar inputs and 1.25V with bipolar inputs. The internal reference voltage is adjustable by 100mV with the circuit in Figure 12. External Reference The MAX1282/MAX1283's external reference can be placed at the input (REFADJ) or the output (REF) of the internal reference-buffer amplifier. The REFADJ input impedance is typically 17k. At REF, the DC input resistance is a minimum of 18k. During conversion, an external reference at REF must deliver up to 350A DC load current and have 10 or less output impedance. If the reference has a higher output impedance or is noisy, bypass it close to the REF pin with a 4.7F capacitor.
Internal and External References
The MAX1282/MAX1283 can be used with an internal or external reference voltage. An external reference can be connected directly at REF or at the REFADJ pin.
Table 5. Full Scale and Zero Scale
UNIPOLAR MODE Full Scale VREF + VCOM Zero Scale VCOM Positive Full Scale VREF / 2 + VCOM BIPOLAR MODE Zero Scale VCOM Negative Full Scale VREF / 2 + VCOM
16
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300ksps/400ksps, Single-Supply, 4-Channel, Serial 12-Bit ADCs with Internal Reference MAX1282/MAX1283
CS
DIN
S CONTROL BYTE 0
S CONTROL BYTE 1
S CONTROL BYTE 2
S
ETC
1 SCLK
8
12
16 1
5
8
12
16 1
5
8
12
16 1
5
DOUT
B11
B6 B0 CONVERSION RESULT 0
B11
B6 B0 CONVERSION RESULT 1
B11
B6
SSTRB
Figure 7. Continuous 16-Clock/Conversion Timing
1.50 REFERENCE POWER-UP DELAY (ms) 1.25 1.00 0.75 0.50 0.25 0 0.0001 SUPPLY CURRENT (A)
10k MAX1283, VDD1 = VDD 2 = 3.0V CLOAD = 20pF CODE = 101010000000 1k 4 CHANNELS 100 1 CHANNEL 10
1 0.001 0.01 0.1 1 10 1 10 100 1k 10k 100k TIME IN SHUTDOWN (s) SAMPLING RATE (sps)
Figure 8. Reference Power-Up Delay vs. Time in Shutdown
Figure 9b. Average Supply Current vs. Conversion Rate with External Reference in FULLPD
2.5
1k MAX1283, VDD1 = VDD2 = 3.0V CLOAD = 20pF CODE = 101010000000 SUPPLY CURRENT (mA)
SUPPLY CURRENT (A)
NORMAL OPERATION 2.0 REDP FASTPD 1.5
100
4 CHANNELS 10 1 CHANNEL
1.0 MAX1283, VDD1 = VDD2 = 3.0V CLOAD = 20pF CODE = 101010000000 0 50 100 150 200 250 300 350
1 0.1 1 10 100 1k 10k SAMPLING RATE (sps)
0.5
SAMPLING RATE (sps)
Figure 9a. Average Supply Current vs. Conversion Rate with Internal Reference in FULLPD
Figure 10. Average Supply Current vs. Sampling Rate (in FASTPD, REDP, and Normal Operation) 17
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300ksps/400ksps, Single-Supply, 4-Channel, Serial 12-Bit ADCs with Internal Reference MAX1282/MAX1283
To use the direct REF input, disable the internal buffer by connecting REFADJ to VDD1. Using the REFADJ input makes buffering the external reference unnecessary. Figure 15 shows the recommended system ground connections. Establish a single-point analog ground (star ground point) at GND. Connect all other analog grounds to the star ground. Connect the digital system ground to this ground only at this point. For lowestnoise operation, the ground return to the star ground's power supply should be low impedance and as short as possible. High-frequency noise in the VDD1 power supply may affect the high-speed comparator in the ADC. Bypass the supply to the star ground with 0.1F and 10F capacitors close to VDD1 of the MAX1282/MAX1283. Minimize capacitor lead lengths for best supply-noise rejection. If the power supply is very noisy, a 10 resistor can be connected as a lowpass filter (Figure 15).
Transfer Function
Table 5 shows the full-scale voltage ranges for unipolar and bipolar modes. Figure 13 depicts the nominal, unipolar input/output (I/O) transfer function, and Figure 14 shows the bipolar I/O transfer function. Code transitions occur halfway between successive-integer LSB values. Output coding is binary, with 1LSB = 0.61mV (2.500V / 4096) for unipolar operation, and 1LSB = 0.61mV [(2.500V / 2) / 4096] for bipolar operation.
Layout, Grounding, and Bypassing
For best performance, use PC boards; wire-wrap boards are not recommended. Board layout should ensure that digital and analog signal lines are separated from each other. Do not run analog and digital (especially clock) lines parallel to one another, or digital lines underneath the ADC package.
High-Speed Digital Interfacing with QSPI
The MAX1282/MAX1283 can interface with QSPI using the circuit in Figure 16 (CPOL = 0, CPHA = 0). This QSPI circuit can be programmed to do a conversion on each of the four channels. The result is stored in memory without taxing the CPU, since QSPI incorporates its own microsequencer.
WAIT 2ms (10 x RC)
1 DIN FULLPD
00
1 REDP
10
1 FULLPD 1.22V
00
1
1.22V RE FADJ 0V 2.5V REF 0V IVDD1 + IVDD2 2.5mA 0mA
DUMMY CONVERSION
= RC = 17k x 0.01F
2.5V
2.5mA 1.3mA OR 0.9mA
2.5mA 0mA
Figure 11a. Full Power-Down Timing
1 DIN REDP
10
1 REDP
10
1 FASTPD
01
REF
2.5V (ALWAYS ON) 2.5mA 2.5mA 0.9mA 0.9mA 2.5mA 1.3mA
IVDD1 + IVDD2
Figure 11b. FASTPD and REDP Timing 18 ______________________________________________________________________________________
300ksps/400ksps, Single-Supply, 4-Channel, Serial 12-Bit ADCs with Internal Reference MAX1282/MAX1283
+3.3V 24k 510k 100k 12 0.047F MAX1282 MAX1283 REFADJ
000 . . . 010 000 . . . 001 000 . . . 000 111 . . . 111 111 . . . 110 111 . . . 101 011 . . . 111 011 . . . 110 OUTPUT CODE FS = VREF + VCOM 2 ZS = VCOM -FS = -VREF + VCOM 2 VREF 4096
1LSB =
Figure 12. MAX1282/MAX1283 Reference-Adjust Circuit
OUTPUT CODE FULL-SCALE TRANSITION
100 . . . 001 100 . . . 000 - FS COM* INPUT VOLTAGE (LSB) *VCOM VREF / 2 +FS - 1LSB
11 . . . 111 11 . . . 110 11 . . . 101
FS = VREF + VCOM ZS = VCOM V 1LSB = REF 4096
Figure 14. Bipolar Transfer Function, Full Scale (FS) = VREF / 2 + VCOM, Zero Scale (ZS) = VCOM
00 . . . 011 00 . . . 010 00 . . . 001 00 . . . 000 01 (COM) 2 3 INPUT VOLTAGE (LSB)
2) The MAX1282/MAX1283's CS pin is driven low by the TMS320's XF_ I/O port to enable data to be clocked into the MAX1282/MAX1283's DIN pin. 3) An 8-bit word (1XXXXX11) should be written to the MAX1282/MAX1283 to initiate a conversion and place the device into normal operating mode. See Table 3 to select the proper XXXXX bit values for your specific application. 4) The MAX1282/MAX1283's SSTRB output is monitored through the TMS320's FSR input. A falling edge on the SSTRB output indicates that the conversion is in progress and data is ready to be received from the device. 5) The TMS320 reads in 1 data bit on each of the next 16 rising edges of SCLK. These data bits represent the 12-bit conversion result followed by 4 trailing bits, which should be ignored. 6) Pull CS high to disable the MAX1282/MAX1283 until the next conversion is initiated.
FS FS - 3/2LSB
Figure 13. Unipolar Transfer Function, Full Scale (FS) = VREF + VCOM, Zero Scale (ZS) = VCOM
TMS320LC3x Interface
Figure 17 shows an application circuit to interface the MAX1282/MAX1283 to the TMS320 in external clock mode. The timing diagram for this interface circuit is shown in Figure 18. Use the following steps to initiate a conversion in the MAX1282/MAX1283 and to read the results: 1) The TMS320 should be configured with CLKX (transmit clock) as an active-high output clock and CLKR (TMS320 receive clock) as an active-high input clock. CLKX and CLKR on the TMS320 are connected to the MAX1282/MAX1283's SCLK input.
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19
300ksps/400ksps, Single-Supply, 4-Channel, Serial 12-Bit ADCs with Internal Reference MAX1282/MAX1283
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital samples, the SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused only by quantization error and results directly from the ADC's resolution (N bits): SNR = (6.02
*R = 10
SUPPLIES +3V GND +3V
N + 1.76)dB
VDD1
GND
COM
VDD2
+3V
DGND
In reality, there are other noise sources besides quantization noise, including thermal noise, reference noise, clock jitter, etc. Therefore, SNR is calculated by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first five harmonics, and the DC offset.
MAX1282 MAX1283
*OPTIONAL
DIGITAL CIRCUITRY
Signal-to-Noise Plus Distortion (SINAD)
SINAD is the ratio of the fundamental input frequency's RMS amplitude to RMS equivalent of all other ADC output signals: SINAD (dB) = 20 log (SignalRMS / NoiseRMS)
Figure 15. Power-Supply Grounding Connection
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values from a straight line on an actual transfer function. This straight line can be a best-straight-line fit or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. The static linearity parameters for the MAX1282/MAX1283 are measured using the best straight-line fit method.
Effective Number of Bits (ENOB)
ENOB indicates the global accuracy of an ADC at a specific input frequency and sampling rate. An ideal ADC's error consists only of quantization noise. With an input range equal to the ADC's full-scale range, calculate ENOB as follows: ENOB = (SINAD - 1.76) / 6.02
Total Harmonic Distortion (THD)
THD is the ratio of the RMS sum of the input signal's first five harmonics to the fundamental itself. This is expressed as: 2 2 2 2 2 V2 + V3 + V4 + V4 + V5 THD = 20 x log V1 where V1 is the fundamental amplitude, and V2 through V5 are the amplitudes of the 2nd- through 5th-order harmonics.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between an actual step width and the ideal value of 1LSB. A DNL error specification of less than 1LSB guarantees no missing codes and a monotonic transfer function.
Aperture Width
Aperture width (tAW) is the time the T/H circuit requires to disconnect the hold capacitor from the input circuit (for instance, to turn off the sampling bridge, and put the T/H unit in hold mode).
Aperture Jitter
Aperture jitter (tAJ) is the sample-to-sample variation in the time between the samples.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest distortion component.
Aperture Delay
Aperture delay (tAD) is the time defined between the rising edge of the sampling clock and the instant when an actual sample is taken.
20
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300ksps/400ksps, Single-Supply, 4-Channel, Serial 12-Bit ADCs with Internal Reference MAX1282/MAX1283
+5V OR +3V 10F 0.1F +5V OR +3V
1 VDD1 2 CH0 3 CH1 4 CH2 5 CH3 VDD1 6 COM 7 SHDN 8 REF
VDD2 16
0.1F 10F (POWER SUPPLIES) SCK
SCLK 15
ANALOG INPUTS
MAX1282 MAX1283
CSB 14 DIN 13 SSTRB 12
PCS0 MOSI
MC683XX
MISO
DOUT 11 GND 10 REFADJ 9
0.01F (GND)
4.7F
Figure 16. QSPI Connections
XF CLKX
CS SCLK
TMS320LC3x
CLKR DX DR FSR
MAX1282 MAX1283
DIN DOUT SSTRB
Figure 17. MAX1282/MAX1283-to-TMS320 Serial Interface
______________________________________________________________________________________
21
300ksps/400ksps, Single-Supply, 4-Channel, Serial 12-Bit ADCs with Internal Reference MAX1282/MAX1283
CS
SCLK START SEL2 SEL1 SEL0 UNI/BIP SGI/DIF PD1 PD0 HIGH IMPEDANCE MSB B10 B1 B0 HIGH IMPEDANCE
DIN SSTRB DOUT
Figure 18. MAX1282/MAX1283-to-TMS320 Serial Interface
Typical Operating Circuit
+5V OR +3V CH0 0 TO +2.5V ANALOG INPUTS VDD1 VDD2 VDD 0.1F
Chip Information
TRANSISTOR COUNT: 4286 PROCESS: BiCMOS
MAX1282 GND MAX1283
CH3 REF COM CS SCLK DIN REFADJ DOUT SSTRB SHDN I/O
CPU
4.7F
SCK (SK) MOSI (SO) MISO (SI) VSS
0.01F
22
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300ksps/400ksps, Single-Supply, 4-Channel, Serial 12-Bit ADCs with Internal Reference
________________________________________________________Package Information
TSSOP.EPS
MAX1282/MAX1283
Note: The MAX1282/MAX1283 do not have an exposed die pad.
______________________________________________________________________________________
23
300ksps/400ksps, Single-Supply, 4-Channel, Serial 12-Bit ADCs with Internal Reference MAX1282/MAX1283
NOTES
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
24 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2000 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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